A 2 channel controller with some specific layout/wiring features. This is targeted at restoring SimonK availability to the FDL-3 (including closed loop adjustable speed developments and whatnot, if desired) and ...at least providing some insurance that they don't HAVE to get their ESCs yanked out from under them again in the future - even if most people keep using COTS BLHeli_32 stuff in their setups for the time being. This version is a discrete drive unit, with LFPAK56 devices.
You can also see the SMPS down there on the right; it's an Alpha/Omega AOZ1282 1.2A output, 36V max input buck which I have found to be a cold running, solid little setup on my S-Core boards. That ought to handle all the logic power requirements (all of which are 5V) in the blaster with some current to spare and run cool enough.
Speaking of
That has always been a point of intense worry of mine, having had some bad experiences early on (and who HASN'T had a frustrating random-reset gremlin at some point?) and although the culprits were a number of other bad things I was doing and stock ESC firmwares were doing at the time, that led me to insist on SEPIC/buck-boost regulators to power blaster managers for the longest time - the idea being that during some horrible bus sag event or negative noise spike, you have a tad more input voltage margin. What led me to reconsider was realizing a few key things:
- Most SEPIC regulators, including ones I used with success, can't actually run down to less than 4.5V or 4.0V anyway. It's a big reg selection, footprint, and cost constraint over... what, half a volt? A volt? A volt and a half of margin gained, absolute max.
- Holy hell, if the DC bus in something DOES ever have more than -10 volts of peak noise, there is a Very Serious Problem going on, and other things like mosfets exposed to that are probably in danger. If there is more than -10 volts of SAG on a longer timescale, that's also a battery that is completely and utterly incapable of powering the load (or maybe mistuned inverters trying to commit suicide with a kabillion amps).
- My ESCs are running on linear LDO regulators without that filter with good success. Never a random reset.
But once burned, twice cautious. Hence this circuit has made it into a few designs, including the S-Core and the current state of the above board:
Note D7 and C16 on the input - this is a negative spike filter of the sort recommended in the datasheet for my favorite LDO linear, the ST L5150BN (which is an automotive-targeted part). The big Schottky diode prevents any negative pulses on the input from sucking charge out of the cap, and the cap caches a bit of sag ride-through energy to use during such a transient. There is a bit of forward drop on the diode but it's a Schottky so not much.
Is it necessary? No. I can say that pretty solidly - all my ESCs, including ones I designed, don't have any such filter. Good decoupling on your MCUs, big enough 5V rail bulk caps, and making sure all motor drives have the proper DC link capacitors fitted does the trick so well that not even an ancient and empty 3S pack causes any resets. But it's peace of mind if this filter fits, and it costs like $2.50. Watch out for inrush current into the cap. Beef the diode, or else do something to mitigate the surge when switching this on. That's why the diode shown is a beefy SMA part rated for Ifsm of 100A (which appears to be enough).
Something interesting is that this circuit is effectively a high-powered version of a peak detector. Could that make a DC bus overvoltage transient more dangerous? Maybe. But momentary overvoltage spikes, if they are present, can still kill a switchmode (or any) reg anyway, so input rating headroom is important (as is trying to avoid noising up your DC bus in the first place). The AOZ1282 is rated for 36V and my go-to linear is 40V. Worst-case worrying me wants to whack a TVS diode on the input of the reg. That's what I did on the Twinverter board where that filter feeds gate drive too - or at least the footprint is there if you are concerned enough to use it. Same with the main diode in fact - that can be a wire instead if you don't want it.
Back to some gate drive matters:
Obsessive me gets to wondering about stuff like...
What is the actual high-side gate voltage level?
Indeed it CAN be that under certain circumstances - namely, if the phase is (or is being driven) low just prior to turning the high-side switch on. This might be occurring often if you are using complementary PWM in which during (assuming HIGH_SIDE_PWM = 0) the off-time, the high-side switch is on.
But in plenty of situations, the phase would be near neutral before getting driven high by turning on the high-side switch, and that case the cap might not be charged to the full voltage.
The bootstrap cap C4...6 and the ballast resistor R11...13 form a RC network. The time constant (time required for about 63% change in voltage after a sudden step) would be of the order of 2ms (2.2 for common boards, 1.6 for mine) with the usual R and C. Given that, at high motor speeds where an entire cycle of the AC waveform could take 0.3ms and thus 0.1ms between high-side drive events and 0.056ms between commutation steps, it's gonna be pretty close to DC bus voltage - but at low speeds, where a single commutation might be 8ms or more (this is one of the main V/Hz inflection points in SimonK current limiting settings), the bootstrap voltage could have time to fall a bit and become more like half DC bus voltage - since the phase is no longer fully low, it's at near neutral.
Right?
Well, not quite... The "neutral point voltage" is a concept that arises out of the AC polyphase nature of the inverter section and motor relative to the "one-sided" (one leg considered the ground reference for logic and gate driving purposes) DC bus. Neutral, and the "Zero" that the phase voltage is crossing and we're sensing (through dividers to put in safe 0-5V range) to know the rotor position, is NOT just half DC bus!! It's half the PHASE voltage. Which is half DC bus at 100% voltage command, but is MUCH less (sixth, quarter, half...) than DC bus voltage at low speed given that your V/Hz (POWER_RANGEx) settings are sane, and are not trying to do high duty cycle into a basically-stopped motor (which is distinctly bad anyway).
The RC filter effect on the bootstrap would just help to make that more true and make the voltage on the cap constantish by averaging out the PWM waveform on the phase voltage which is at 5-20+ kHz per settings.
So the voltage across the cap (bus minus neutral, roughly) is bound to be higher than half-bus in practice at low speed. And by the time a drive is at a speed range where it can safely open up at 100% duty and put the neutral to half-bus level (stock SimonK: 1ms/commutation, my tune: 0.8ms), it's already about to be less than one time constant and so perhaps 70% of bus is more appropriate a guess than 50%. That would have plenty of margin for 4.5V design mosfets.
But wait there's more
Remember when I mentioned that discrete drivers don't have UVLO? Well, they DO have UVLO assuming you keep one bit of the original "Hobbytroller" design tenets I find rather clever.
The logic power is normally derived by a ~0.5V dropout LDO or switchmode buck (not -boost) regulator from the DC bus voltage (which of course charges the bootstraps up). The AVR has its brownout detector enabled and set to hold the chip on reset at about 4.0V (as operation below here at 16MHz is out of spec and risks crashing).
Bang. There's your undervoltage lockout. For ALL the gate drivers.
Just use mosfets spec'd for 4.5V gate drive levels.
Plenty of considerations going on with these "crude" "janky" "cheapo" gate drive circuits, huh? They're clever, brutal, elegant and awesome. Dronepeople might want to bash them, but they're actually far more well thought through than I realized early on. ("Can anyone show us a discrete drive board that failed in a manner that a driver-equipped one wouldn't have?" Crickets, most likely.)
Now there's another gotcha. You don't want to do anything (such as, um, wiring it to an external 5V supply... like I did back several years in an old project) that prevents critical (<4.5 ish V) DC bus dips from disabling the AVR - because then you just disabled your UVLO. IF you want to do something to stabilize, filter or de-sag logic power, you must ALSO stabilize the gate drive rail feeding the bootstrap diodes AND there must be a BUCK regulator feeding the MCU off that so that its brownout detect trips if the gate drive collapses. See the Twinverter? Look where the gate drive rail comes from. Yep - The input filter.
Bootstrap diodes. Hmmmm....
Most ESC boards have 1N4148 or similar for the bootstraps, whether discrete or with gate drivers that require external diodes (most of them including the now popular Fortior FD6288 and the old school IR2101). Often, the 4148 is or was a distinctive glass-passivated MiniMELF style that you will see on ZTW boards. On Afros, it's a damn tiny SOD-323 or -523 or something (looks like an 0603 scale thing). On my ACE LC1, I have spec'd a 4148 as well. Is there a better choice?
Well, first off, they need to be fast enough to switch on and recharge the cap effectively at high drive frequencies, so not some slow clumsy rectifier. And they must have as little reverse leakage as possible, since there is NO supply besides the cap to support the gate voltage during an on-time. The 1N4x48 series cover those pretty well.
What the hell kind of pulsed current do these need to withstand? There's a circa 1uF ceramic capacitor that it's feeding. Seems like a potential inrush issue. That's my main worry point.
At switch-on, the phase nodes are not clamped low - the low side switches are off and the phases floating. The phases might be pinned high if the bootstraps were still charged from the last power-up, but once the MCU turns on they will shut off. At this point, there is a current path for charging the cap fully which is through the sense voltage divider resistors, which are pulling the phases down to ground. That 18k + 3.3k is a nice soft-start precharge for the caps. By the time we're trying to drive, they have long ago filled up (3 time constants are ~60ms). So startup from cold, that's OK.
While running would be a more aggressive case perhaps:
- Phase driven high. Cap, gate and ballast node sitting above DC bus by however much. Transistor off. Diode blocking gate/cap voltage against returning to the DC bus.
- High-side signal goes back high (=off). Transistor turns on. Gate plummets and the mosfet turns off.
- Cap voltage does NOT plummet with the gate. The ballast resistor is between the cap and gate and is too high impedance for it to discharge during the switch-off time so it only drains a little.
- As the phase node swings down toward neutral, one end of the cap also does, eventually as the phase is driven low the other end of the cap that had charged the gate crosses below the DC bus level and the diode starts conducting, charging the cap.
So it's however much charge bled off from the gate leakage, the diode leakage, the leakage through 1.6K resistor during the switch-off time of the fet which is pretty snappy (few hundred ns ish?) that is being "refilled" at a rate controlled by the slew rate of the phase voltage. I need myself a scope right about now to get numbers off real boards...
4148s appear to never die here and they are in many gate driver datasheets as a bootstrap diode with ~1uF bootstrap caps. But I am going to spec 1N4448 going forward. Unlike 4148s which can be EITHER 2A or 4A pulse rated per manufacturer, 4448 are always 4A. There are both SOD-123 and MiniMELF versions of 4448 to suit your preference and they are cheaper than dirt just like 4148s. This is probably a "Don't fix what ain't broken" situation. Most Schottkys are either higher leakage or have equivalent or worse pulse current ratings.
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